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LIVE AT DAC
Tech talk show | Cadence events | Industry alliances | Cadence Conference speakers
Find out why customers collaborate with Cadence to solve their design challenges. In the Cadence booth, you'll see compelling new technology and flow demos, and you'll have a chance to talk with our technical experts about the hottest topics. With Cadence technology, you'll create faster, cooler, more complex designs from concept to manufacturing.
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Cadence technologists, customers, and partners will be on stage and screen discussing the topics that interest you most, from today's design challenges to tomorrow's design possibilities. Meet with these industry luminaries and find
out how you can achieve breakthrough results.
*Schedule subject to change
MONDAY, JUNE 13
High-performance digital
Time: 9:30am
Topic: Implementation solution for 90nm, high-performance multimedia
Customer: Sylvain Duvillard, Philips Semiconductors
Functional verification
Time: 10:00am
Topic: Using Incisive technology to validate the most complex designs
Customer: Narendra Konda, NVIDIA
Technologist: Mikhail Bershteyn, Cadence
Digital IC design
Time: 10:30am
Topic: Advanced synthesis technology
Customer: Maynard Hammond, Scientific-Atlanta
Partner: Philip Watson, ARM
Technologist: Pradeep Fernandes, Cadence
Functional verification
Time: 11:00am
Topic: Overcoming verification bottlenecks for complex multimedia SoCs
Customer: Thierry Bauchon, STMicroelectronics
Technologist: Michael McNamara, Cadence
Custom design
Time: 11:30am
Topic: Fast and accurate mixed-signal design simulation
Customer: Jose Mena, Texas Instruments
Technologist: Peter Frey, Cadence
Silicon-package-board co-design
Time: 1:00pm
Topic: Multi-gigabit channel design methodology
Customer: Mike Resso, Agilent Technologies
Customer: James Smith, Altera
Technologist: Brad Griffin, Cadence
Custom design
Time: 1:30pm
Topic: Custom layout process migration and optimization
Customer: Jee-Hoon Krska, Agere Systems
Technologist: Randy Fish, Cadence
Silicon-package-board co-design
Time: 2:00pm
Topic: Accelerating package design to manufacturing
Customer: Nozad Karim, Amkor Technology
Technologist: Brad Griffin, Cadence
Technology discussion with industry luminary
Time: 2:30pm
Technologist: Ted Vucurevich, Cadence
Digital IC design
Time: 3:00pm
Topic: Implementation solution for 90nm, high-performance multimedia design
Customer: Sylvain Duvillard, Philips Semiconductors
Chip interconnect IP
Time: 3:30pm
Topic: Tackling the challenges of incorporating high-speed serial links
Partner: Stefan Tamme, Rambus
Technologist: Rob Rouland, Cadence
Functional verification
Time: 4:00pm
Topic: Design verification using formal technology
Technologist: Kei-Yong Khoo, Cadence
Time: 4:30pm
Functional verification
Topic: Assertion-based verification language standards development
Technologist: Erich Marschner, Cadence
TUESDAY, JUNE 14
Functional verification
Time: 9:30am
Topic: Assertion-based verification language standards development
Technologist: Erich Marschner, Cadence
Silicon-package-board co-design
Time: 10:00am
Topic: Accelerating package design to manufacturing
Customer: Nozad Karim, Amkor Technology
Technologist: Brad Griffin, Cadence
Custom design
Time: 10:30am
Topic: Fast and accurate mixed-signal design simulation
Customer: Jose Mena, Texas Instruments
Technologist: Peter Frey, Cadence
Time: 11:00am
Topic: Technology discussion with industry luminary, Ted Vucurevich
Technologist: Ted Vucurevich, Cadence
Custom design
Time: 11:30am
Topic: Custom layout process migration and optimization
Customer: Jee-Hoon Krska, Agere Systems
Technologist: Randy Fish, Cadence
Wireless/Custom design
Time: 1:00pm
Topic: Wireless infrastructure and solutions
Partner: Jim Mecke, IBM
Technologist: Juergen Hartung, Cadence
Custom design
Time: 1:30pm
Topic: Surface potential versus charge sheet modeling
Customer: Mats Lindstrom, Conexant Systems
Partner: James Victory, Jazz Semiconductor
Technologist: Zhihong Liu, Cadence
Digital IC design
Time: 2:00pm
Topic: Advanced synthesis technology
Customer: Russell Petersen, Scientific-Atlanta
Partner: Philip Watson, ARM
Technologist: Pradeep Fernandes, Cadence
Time: 2:30pm
Topic: Technology discussion with industry luminary Alberto Sangiovanni-Vincentelli
Technologist: Alberto Sangiovanni-Vincentelli, Cadence
Custom design
Time: 3:00pm
Topic: Custom layout process migration and optimization
Customer: Jee-Hoon Krska, Agere Systems
Technologist: Randy Fish, Cadence
Silicon-package-board co-design
Time: 3:30pm
Topic: Why model and simulate complex IC die-stack packages in 3D?
Customer: Greg Fitzgerald, Optimal Corporation
Technologist: Keith Felton, Cadence
Functional verification
Time: 4:00pm
Topic: Overcoming verification bottlenecks for complex multimedia SoCs
Customer: Thierry Bauchon, STMicroelectronics
Technologist: Michael McNamara, Cadence
Digital IC design
Time: 4:30pm
Topic: Test challenges for nanometer designs
Partner: Magdy Abadir, Freescale Semiconductor
Technologist: Mick Tegethoff, Cadence
WEDNESDAY, JUNE 15
Silicon-package-board co-design
Time: 9:30am
Topic: Why model and simulate complex IC die-stack packages in 3D?
Customer: Greg Fitzgerald, Optimal Corporation
Technologist: Keith Felton, Cadence
Functional verification
Time: 10:00am
Topic: Managing multi-language verification methodology and functional coverage
Customer/Partner: Alan Hunter, ARM
Technologist: Michael McNamara, Cadence
Wireless
Time: 10:30am
Topic: Wireless IC design
Customer: Bill Frede, ZMD
Technologist: Coby Yasha, Cadence
Time: 11:00am
Topic: Technology discussion with industry luminary Alberto Sangiovanni-Vincentelli
Technologist: Alberto Sangiovanni-Vincentelli, Cadence
Functionl verification
Time: 11:30am
Topic: Using Incisive technology to validate the most complex designs
Customer: Narendra Konda, NVIDIA
Technologist: Mikhail Bershteyn, Cadence
Digital IC design
Time: 1:00pm
Topic: Test challenges for nanometer designs
Partner: Dr. Rob Aitken, ARM
Technologist: Mick Tegethoff, Cadence
Functional verification
Time: 1:30pm
Topic: Assertion-based verification language standards development
Technologist: Erich Marschner, Cadence
Custom design
Time: 2:00pm
Topic: Fast and accurate mixed-signal design simulation
Customer: Jose Mena, Texas Instruments
Technologist: Peter Frey, Cadence
Chip interconnect IP
Time: 2:30pm
Topic: Tackling the challenges of incorporating high-speed serial links
Partner: Stefan Tamme, Rambus
Technologist: Rob Rouland, Cadence
Silicon-package-board co-design
Time: 3:00pm
Topic: Multi-gigabit channel design methodology
Customer: Greg Peters, Agilent Technologies
Customer: James Smith, Altera
Technologist: Brad Griffin, Cadence
Time: 3:30pm
Topic: Technology discussion with industry luminary, Ron Rohrer
Technologist: Ron Rohrer, Cadence
Wireless
Time: 4:00pm
Topic: Wireless infrastructure and solutions
Partner: Jim Mecke, IBM
Technologist: Juergen Hartung, Cadence
Yield
Time: 4:30pm
Topic: Design for yield
Partner: Kevin MacLean, PDF Solutions
Technologist: Vassilios Gerousis, Cadence
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TUESDAY, JUNE 14, 2005
The Annual X Initiative Anniversary Breakfast
Time: 7:30am
Location: Anaheim Convention Center, Ballroom D
Register now.
The X Initiative, a consortium co-sponsored by Cadence, is focused on accelerating the adoption and fabrication of X Architecture. This annual breakfast event at DAC serves as a platform to present the latest X Architecture silicon results and news, and to celebrate the X Initiative's collaborative work. At the event, the consortium will honor the year's recipient of the X Initiative Design-to-Manufacturing Catalyst Award, presented to the X Initiative member company that has made the greatest contribution toward making the X Architecture successful and bridging the gap between design and manufacturing. Visit www.xinitiative.com for more information.
Cadence Functional Verification Luncheon: The Latest in Verification Process Automation
Time: 11:30am-2pm
Location: Anaheim Convention Center, Ballroom D
Register now.
Join Moshe Gavrielov, executive vice president of the new Cadence verification division, and industry-leading customers for an interactive discussion on what is required for verifying today's complex designs. Targeted to design and verification managers and engineers, this luncheon will present the new vision and strategy of the combined Cadence and Verisity organizations. Agere, ARM and ST will share how they developed and leveraged successful verification plans that accelerated their design and verification cycle to produce high-quality, first-working silicon and software. Attendees can enter to win a Garmin handheld GPS receiver!
WEDNESDAY, JUNE 15, 2005
Accellera Breakfast and Panel Discussion: Design and Verification—Bridging the Chasm
Moderator: Steve Ohr, Analog Editor, CMP
Time: 7:30am-9:00am
Location: Anaheim Hilton, Capistrano A
Register now.
Historically, the design and verification functions in the development of an SoC design have remained a proverbial "tale of two cities." The needs and the tasks of the design team overlap minimally with that of the verification team. The tools and methodologies developed for each of these functions differ in many ways. With the tremendous pressure to create complex yet robust designs in shorter periods of time, there is an increasing need to address how useful and necessary information is readily available for either teams to use. In addition to this, we need to consider how AMS standards can help create placeholders for this information to be provided, updated, and reused in an efficient and relatively easy manner. This session will consider the different bridges—tools, methodologies, and standards—that will alleviate and simplify the tasks of design and verification teams.
Cadence/IBM Breakfast: Is ASIC the Answer for 65NM?
Time: 7:30am-9:00am
Location: Anaheim Convention Center, Ballroom D
Register now.
The industry has seen a trend toward COT in the last decade. The ASIC market has seen cyclical behavior trending toward flat or negative growth. With the increasing contributions from consumer electronics to the growth of the semiconductor industry, as well as the increasing cost and complexity of design and manufacturing at 90nm, 65nm, and below, will the ASIC model be the better option? In the ASIC environment, the handoff between the customer and the ASIC provider has also gotten complex, increasing the number of iterations due to implementation issues, which affects product delivery. Can better design software, support, and libraries help mitigate that?
DAC Solutions Workshop and Luncheon: Transaction-level Modeling using e, SystemC, and SystemVerilog in a Unified Verification Environment
Time: 11:30am-2:00pm
Location: Anaheim Convention Center, Room 204C
Register now.
Today's functional verification environments typically require multiple languages for design and verification. Virtual prototypes using transaction-level models (TLMs) serve as a starting point for a structured functional verification flow, and languages like e, SystemC, and SystemVerilog can be leveraged to maximize productivity for different tasks within the flow. Presented by Cadence and Doulos, this workshop gives an overview of transaction-level modeling for architectural exploration as exemplified by SystemC, and for functional verification as exemplified by e. You'll hear the latest on e language (IEEE P1647) standardization and how it incorporates new features for interoperability with SystemC and SystemVerilog at the transaction level.
THURSDAY, JUNE 16, 2005
Silicon Design Chain Breakfast: Power Management Collaboration Results
Time: 7:30am - 9:00am
Location: Anaheim Convention Center, Ballroom D
Register now.
Power management is a growing concern for nearly all designs at 90nm and below. Industry leaders Applied Materials, ARM, Cadence, and Taiwan Semiconductor Manufacturing Corporation (TSMC), working together through the Silicon Design Chain Initiative, will discuss how their 90nm test chip project resulted in a new, silicon-validated power management approach that can reduce overall chip power consumption by 40%. This approach will enable a broad range of designers to apply sophisticated low-power design techniques to complex SoCs.
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ACCELLERA Booth 2284
Understand how SystemVerilog can be used in a multi-language environment throughout the design and verification cycle of semiconductor design. Cadence will show how the Incisive verification platform and the Encounter digital IC design platform support SystemVerilog, Verilog, VHDL, SystemC, and e languages in an integrated design and verification environment. The presentation features Incisive Unified Simulator, Incisive Formal Verifier, Encounter RTL Compiler, and Encounter Conformal technology.
INTEL Booth 2291
Visit the Intel booth to see three Cadence product demos. Learn how to improve synthesis runtimes without sacrificing results using Cadence Encounter RTL Compiler synthesis running on a 64-bit Intel Xeon processor-based computing platform (56 processor blade configuration RACK system). Find out how to route a flat 90nm, 16M-gate systolic array medical imaging processor 20 times faster using Cadence NanoRoute™ router running on both a 64-bit Intel Xeon processor-based computing platform (80 processor RACK system) and a 64-bit Intel Xeon MP-based computing platform. Discover how to increase verification performance for mixed-signal designs through the integration of Virtuoso UltraSim Full-chip Simulator with Virtuoso AMS Designer technology, running on both a 64-bit Intel Xeon processor-based computing platform and an Intel Centrino mobile technology-based laptop workstation.
Si2 Booth 1840
Experience the power of OpenAccess in real-time! You'll see translation-free interoperability for real-world design in two specific design tasks: 1) Optimized pad placement for the redistribution layer required for die bonding using Cadence Allegro Package Designer and the Encounter digital IC design platform; and 2) ECO implementation involving both logical and physical design changes using the Encounter platform and the Virtuoso custom design platform.
UMC Booth 1801
See a digital reference flow targeting SoC designs at 130nm and below. Ideal for both wired and wireless applications, this RTL-to-GDSII flow takes advantage of UMC's leading-edge technology that enables high-speed and low-power IC design with a predictable path to silicon.
VIRAGE LOGIC Booth 406 and 412
Visit the Virage Logic booth to see two Cadence demos. Low-power design flow: See how you can achieve 40% total power savings with the Cadence low-power design flow. Nanometer delay modeling with ECSMs: High-performance, low-power nanometer-scale designs face new challenges for timing and delay calculation. Adopting leading-edge delay models such as effective current source models (ECSMs) is vital to help design teams achieve timing predictability. This technical presentation elaborates on the emerging ECSM standard and the growing support for this modeling format.
WIRELESS SHOWCASE Booth 1968
Consumer demand for smaller form factors and increased functionality is driving wireless design teams to ever higher levels of IC integration and performance. Come to the Wireless Showcase and hear from Cadence technologists, partners, and customers about solving today's wireless design challenges, including: system-to-IC implementation, mixed-mode simulation and verification, parasitic extraction, signal integrity analysis, and hardware/software co-design. Learn how the latest technology is being applied to wireless designs to reduce product development risk and cost while speeding time-to-market.
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MONDAY, JUNE 13, 2005
Pavilion Panel: EDA—Why Invest?
Jennifer Jordan, Corporate VP, Controller
11:00am-12 noon
Booth 2269
Pavilion Panel: Ask the CTO—Everything You Wanted to Know But Were Afraid to Ask
Ted Vucurevich, Chief Technology Officer
1:00pm-2:00pm
Booth 2269
Pavilion Panel: EDA Serial Acquirees—You Can Run, But You Can't Hide
Veronica Watson, Group Director, Verification Sales
3:00pm-4:00pm
Booth 2269
TUESDAY, JUNE 14, 2005
Session 1.1 CEO panel: Differentiate and Deliver—Leveraging Your Design and Manufacturing Partners From Product Concept to Production
Michael J. Fister, President and CEO
10:30am-12 noon
Room 207ABC
Session 7: Statistical Timing Analysis
Chair: Vinod Kariat, Engineering Group Director, Future Incubations
2:00pm-4:00pm
Room 210CD
Pavilion Panel: The Real Cost of Linux
Mark Noneman, VP of Worldwide Quality
4:00pm-4:45pm
Booth 2269
WEDNESDAY, JUNE 14, 2005
Session 16.2: Explaining the Gap Between ASIC and Custom Power—A Custom Perspective
Andrew Chang, Sr. Services Project Manager, Solutions Architecture
8:30am-10:00am
Room 207ABC
THURSDAY, JUNE 16, 2005
Session 40: Circuit Performance Under Parameter Variation
Chair: L. Miguel Silveira, INESC-ID/IST/Cadence Labs, Lisbon, Portugal
8:30am-10:00am
Room 208AB
Session 45.4: Dynamic Abstraction Using SAT-based BMC
Liang (Gordon) Zhang, Sr. Member of the Technical Staff, Functional Verification R&D
10:30am-12 noon
Room 208AB
Pavilion Panel: Software Piracy—Can the EDA Industry Survive It?
Larry Disenhof, Facilities/Real Estate Director
12 noon-12:45pm
Booth 2269
Keynote: Innovation in the EDA Business Need Not Be an Oxymoron
Ronald A. Rohrer, Corporate VP, R&D, High-performance Design
12:45pm-1:45pm
Ballroom ABC
FRIDAY, JUNE 17, 2005
Tutorial 5: Design for Manufacturing at 65nm and Below
Lou Scheffer, Cadence Fellow, IC Solutions
9:00am-5:00pm
Room: 209AB
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